Practical VHDL optimization for timing critical FPGA applications

K. Kuusilinna, T. Hämäläinen, J. Saarinen

    Research output: Contribution to journalArticleScientificpeer-review

    4 Citations (Scopus)
    Translated title of the contributionPractical VHDL optimization for timing critical FPGA applications
    Original languageEnglish
    Pages (from-to)459-469
    JournalMicroprocessors and Microsystems
    Issue number23
    Publication statusPublished - 1999
    Publication typeA1 Journal article-refereed

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