Programmable and Scalable Architecture for Graphics Processing Units

Carlos S. de La Lama; Pekka Jääskeläinen; Heikki Kultala; Jarmo Takala

doi:10.1007/978-3-662-58834-5_2

Programmable and Scalable Architecture for Graphics Processing Units

Carlos S. de La Lama, Pekka Jääskeläinen, Heikki Kultala, Jarmo Takala

Computing Sciences

Research output: Chapter in Book/Report/Conference proceeding › Chapter › Scientific › peer-review

Abstract

Graphics processing is an application area with high level of parallelism at the data level and at the task level. Therefore, graphics processing units (GPU) are often implemented as multiprocessing systems with high performance floating point processing and application specific hardware stages for maximizing the graphics throughput.

In this paper we evaluate the suitability of Transport Triggered Architectures (TTA) as a basis for implementing GPUs. TTA improves scalability over the traditional VLIW-style architectures making it interesting for computationally intensive applications. We show that TTA provides high floating point processing performance while allows more programming freedom than vector processors.

Finally, one of the main features of the presented TTA-based GPU design is its fully programmable architecture making it a suitable target for general purpose computing on GPU APIs which have become popular in the recent years.

Original language	English
Title of host publication	Transactions on High-Performance Embedded Architectures and Compilers V
Editors	Per Stenström, Cristina Silvano, Koen Bertels, Mike Schulte
Pages	21-38
ISBN (Electronic)	978-3-662-58834-5
DOIs	https://doi.org/10.1007/978-3-662-58834-5_2
Publication status	Published - 23 Feb 2019
Publication type	A3 Book chapter

Publication series

Name	Lecture Notes in Computer Science
Publisher	Springer
Volume	11225
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

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Publication forum level 1

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Cite this

de La Lama, C. S., Jääskeläinen, P., Kultala, H., & Takala, J. (2019). Programmable and Scalable Architecture for Graphics Processing Units. In P. Stenström, C. Silvano, K. Bertels, & M. Schulte (Eds.), Transactions on High-Performance Embedded Architectures and Compilers V (pp. 21-38). (Lecture Notes in Computer Science; Vol. 11225). https://doi.org/10.1007/978-3-662-58834-5_2

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Programmable and Scalable Architecture for Graphics Processing Units. / de La Lama, Carlos S.; Jääskeläinen, Pekka; Kultala, Heikki et al.
Transactions on High-Performance Embedded Architectures and Compilers V. ed. / Per Stenström; Cristina Silvano; Koen Bertels; Mike Schulte. 2019. p. 21-38 (Lecture Notes in Computer Science; Vol. 11225).

Research output: Chapter in Book/Report/Conference proceeding › Chapter › Scientific › peer-review

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AB - Graphics processing is an application area with high level of parallelism at the data level and at the task level. Therefore, graphics processing units (GPU) are often implemented as multiprocessing systems with high performance floating point processing and application specific hardware stages for maximizing the graphics throughput.In this paper we evaluate the suitability of Transport Triggered Architectures (TTA) as a basis for implementing GPUs. TTA improves scalability over the traditional VLIW-style architectures making it interesting for computationally intensive applications. We show that TTA provides high floating point processing performance while allows more programming freedom than vector processors.Finally, one of the main features of the presented TTA-based GPU design is its fully programmable architecture making it a suitable target for general purpose computing on GPU APIs which have become popular in the recent years.

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A2 - Silvano, Cristina

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Programmable and Scalable Architecture for Graphics Processing Units

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