Reconfigurable Approximating Accelerators for Edge Computing

Edge computing is one of the key technologies for tackling the growing rate of data production and connectivity demands in Internet of Things (IoT) devices. Distributed edge devices often have constrained computational capabilities and energy availability but must deliver high performance in various applications. This balance requires hardware acceleration and has recently motivated the exploitation of the error tolerance of many target applications through deliberate Approximate Computing (AxC). Approximation adds the output quality as a third angle to the traditional time-energy trade-off spectrum, with associated constraints that a device must adapt to at run-time. However, given their constrained nature, edge devices cannot accommodate several accelerators or programmable architectures. Instead, the integrated accelerator should be reconfigurable to maintain sufficient performance and adaptability while maximizing the benefits of AxC.

This thesis aims to provide insights into the potential hardware overheads and power benefits of integrating adaptive inexact arithmetic into Coarse-Grained Reconfigurable Arrays (CGRAs), which provide word-level reconfigurability accessible through compiler-like tooling. These architectures and AxC techniques are selected by reviewing the related literature from the last decade. The thesis contributes to the AxC field with several libraries for applied research with hardware descriptions of recent inexact arithmetic units, including two novel runtime-configurable inexact adders and multipliers with support for several approximation modes; features for characterization or verification of the error properties of approximate hardware designs; and automated approximation of application kernels mapped to generic CGRA architectures. Each of these libraries fills a gap in the open-source sphere. Their conjunction enables a more efficient design space exploration and lowers the barrier of entry into AxC research with CGRAs.

The thesis further provides initial results from three experiments with the proposed libraries focused on the error characteristics of various inexact adders and multipliers, and the area and power impact of integrating runtime-configurable inexact arithmetic into architecturally diverse CGRAs. The first experiment shows that the proposed inexact arithmetic units have error characteristics – error rate, mean error distance, and mean relative error distance – comparable to those of existing designs and error distributions that can be assumed to be normal with zero mean. The second experiment shows the relatively limited area impact of these units, with four popular CGRAs growing by 7.83% on average. The final experiment shows that the units enable several quality-power operating points despite these additional costs, with an illustrative CGRA achieving up to 14.9% reduced power consumption over an exact baseline when executing a use-case application kernel.