TY - GEN
T1 - Reconfigurable Signal Processing and DSP Hardware Generator for 5G Transmitters
AU - Ghosh, Agnimesh
AU - Spelman, Andrei
AU - Cheung, Tze Hin
AU - Boopathy, Dhanashree
AU - Unnikrishnan, Vishnu
AU - Lampu, Vesa
AU - Xu, Guixian
AU - Anttila, Lauri
AU - Stadius, Kari
AU - Kosunen, Marko
AU - Ryynänen, Jussi
N1 - Funding Information:
This work has received funding from the European Union's Horizon 2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No. 860921 (SMArT), and the Academy of Finland.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - To impose the reconfigurability and reusability of digital circuits for millimeterwave transmitter architectures, high-speed digital signal processing architectures are explored. The digital front-end of these next-generation transmitters can be implemented up to the maximum operating frequency to meet the requirements of the 5G NR FR2 frequency bands. This paper presents an efficient implementation of a reconfigurable digital signal processor (DSP) that contains programmable multistage multirate filters, operable up to 4 GHz, and a flexible generator for polar, outphasing, and multilevel outphasing modulation. The system achieves an excellent ACLR of 42 dB and EVM degradation of 1.61% with a 7-bit phase signal at a sampling frequency of 4 GHz for outphasing modulation. Digital synthesis of the circuit in a 22 nm FDSOI process results in a core area of 0.12 mm2and an estimated power consumption of 142 mW for a 200 MHz bandwidth 5G NR baseband signal.
AB - To impose the reconfigurability and reusability of digital circuits for millimeterwave transmitter architectures, high-speed digital signal processing architectures are explored. The digital front-end of these next-generation transmitters can be implemented up to the maximum operating frequency to meet the requirements of the 5G NR FR2 frequency bands. This paper presents an efficient implementation of a reconfigurable digital signal processor (DSP) that contains programmable multistage multirate filters, operable up to 4 GHz, and a flexible generator for polar, outphasing, and multilevel outphasing modulation. The system achieves an excellent ACLR of 42 dB and EVM degradation of 1.61% with a 7-bit phase signal at a sampling frequency of 4 GHz for outphasing modulation. Digital synthesis of the circuit in a 22 nm FDSOI process results in a core area of 0.12 mm2and an estimated power consumption of 142 mW for a 200 MHz bandwidth 5G NR baseband signal.
KW - 5G
KW - Digital Front-end
KW - Digital signal processing
KW - Reconfigurable Hardware
KW - System on Chip
U2 - 10.1109/NorCAS57515.2022.9934696
DO - 10.1109/NorCAS57515.2022.9934696
M3 - Conference contribution
AN - SCOPUS:85142432958
T3 - 2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings
BT - 2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings
A2 - Nurmi, Jari
A2 - Wisland, Dag T.
A2 - Aunet, Snorre
A2 - Kjelgaard, Kristian
PB - IEEE
T2 - IEEE Nordic Circuits and Systems Conference
Y2 - 25 October 2022 through 26 October 2022
ER -