Revisiting GRAND via High Level Synthesis

Guessing Random Additive Noise Decoding (GRAND) is a recently proposed universal decoding technique for short linear block codes. GRAND-based hardware implementations range from those aimed at low resource utilization at the expense of higher decoding latency to those aimed at achieving low latency at the cost of higher resource utilization. To the best of our knowledge, this work offers the first High-Level Synthesis (HLS)-based open-source hardware implementation framework for GRAND. The proposed framework simplifies Design Space Exploration (DSE) for GRAND hardware implementation and facilitates selecting the implementation parameters to achieve the optimal tradeoff between the decoding latency and hardware resources. The HLS-based framework is employed for developing the baseline hard-input GRAND hardware, and the VLSI architecture is modified to increase the parallelization factor. Hardware implementation results demonstrate that improved GRAND with a parallelization factor of 4 requires 34% more hardware resources; however, the worst-case decoding latency is 14× the latency of the baseline GRAND.