TY - GEN
T1 - Run-to-Completion versus Pipelined
T2 - IEEE International Conference on High Performance Switching and Routing
AU - Zolfaghari, Hesam
AU - Mustafa, Haseeb
AU - Nurmi, Jari
N1 - Funding Information:
ACKNOWLEDGMENT TETRAMAX H2020 project (#761349) is thanked for the support on the technology transfer of our packet processing architecture. We also acknowledge the research grant provided by The Industrial Research Fund at Tampere University of Technology.
Publisher Copyright:
© 2021 IEEE.
jufoid=72023
PY - 2021/6/7
Y1 - 2021/6/7
N2 - Packet parsing is the initial step in processing of network packets. It is encountered in any environment in which packets must be processed. Examples include switches, routers, firewalls, and kernel of operating system. In recent years, there has been focus on programmable and protocol-independent packet processing hardware. The two main hardware architectures for packet processing are run-to-completion and pipelined organization of functional units. This applies to packet parsing as well. Both run-to-completion and pipelined organization have pros and cons and the debate as to which provides greater overall benefit is endless. In this paper, we consider this problem from the perspective of programmable 100 Gbps packet parsing. We will see that the pipelined parser provides 40x throughput compared to the run-to-completion architecture despite running at the same operating frequency and using the same functional units in each pipeline stage.
AB - Packet parsing is the initial step in processing of network packets. It is encountered in any environment in which packets must be processed. Examples include switches, routers, firewalls, and kernel of operating system. In recent years, there has been focus on programmable and protocol-independent packet processing hardware. The two main hardware architectures for packet processing are run-to-completion and pipelined organization of functional units. This applies to packet parsing as well. Both run-to-completion and pipelined organization have pros and cons and the debate as to which provides greater overall benefit is endless. In this paper, we consider this problem from the perspective of programmable 100 Gbps packet parsing. We will see that the pipelined parser provides 40x throughput compared to the run-to-completion architecture despite running at the same operating frequency and using the same functional units in each pipeline stage.
KW - packet parsing
KW - pipeline
KW - Run-to-completion
U2 - 10.1109/HPSR52026.2021.9481797
DO - 10.1109/HPSR52026.2021.9481797
M3 - Conference contribution
AN - SCOPUS:85113876570
T3 - IEEE International Conference on High Performance Switching and Routing, HPSR
BT - 2021 IEEE 22nd International Conference on High Performance Switching and Routing, HPSR 2021
PB - IEEE
Y2 - 7 June 2021 through 10 June 2021
ER -