Simplified Floating-Point Division and Square Root

Timo Viitanen; Pekka Jääskeläinen; Otto Esko; Jarmo Takala

Simplified Floating-Point Division and Square Root

Timo Viitanen, Pekka Jääskeläinen, Otto Esko, Jarmo Takala

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

17 Citations (Scopus)

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Abstract

Digital Signal Processing (DSP) algorithms on low-power embedded platforms are often implemented using ﬁxed-point arithmetic due to expected power and area savings over ﬂoating-point computation. However, recent research shows that ﬂoating-point arithmetic can be made competitive by using a reduced-precision format instead of, e.g., IEEE standard single precision, thereby avoiding the algorithm design and implementation difﬁculties associated with ﬁxed-point arithmetic. This paper investigates the effects of simpliﬁed ﬂoating-point arithmetic applied to an FMA-based ﬂoating-point unit and the associated software division and square root operations. Software operations are proposed which attain near-exact precision with twice the performance of exact algorithms and resolve overﬂow-related errors with inexpensive exponent-manipulation special instructions.

Translated title of the contribution	Simplified Floating-Point Division and Square Root
Original language	English
Title of host publication	IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2013, Vancouver, Canada, May 26-31, 2013
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	2707-2711
Number of pages	5
ISBN (Print)	978-1-4799-0356-6
Publication status	Published - 2013
Publication type	A4 Article in conference proceedings
Event	IEEE International Conference on Acoustics, Speech and Signal Processing - Duration: 1 Jan 1900 → 1 Jan 2000

Publication series

Name	IEEE International Conference on Acoustics, Speech, and Signal Processing
ISSN (Print)	1520-6149

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Conference	IEEE International Conference on Acoustics, Speech and Signal Processing
Period	1/01/00 → 1/01/00

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Publication forum level 1

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Viitanen simplified floating point division and square root
Copyright 2013 IEEE. Published in the IEEE 2013 International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2013), scheduled for 26-31 May 2013 in Vancouver, British Columbia, Canada. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE. Contact: Manager, Copyrights and Permissions / IEEE Service Center / 445 Hoes Lane / P.O. Box 1331 / Piscataway, NJ 08855-1331, USA. Telephone: + Intl. 908-562-3966.

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Viitanen, T., Jääskeläinen, P., Esko, O., & Takala, J. (2013). Simplified Floating-Point Division and Square Root. In IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2013, Vancouver, Canada, May 26-31, 2013 (pp. 2707-2711). (IEEE International Conference on Acoustics, Speech, and Signal Processing). IEEE. http://www.icassp2013.com/

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title = "Simplified Floating-Point Division and Square Root",

abstract = "Digital Signal Processing (DSP) algorithms on low-power embedded platforms are often implemented using ﬁxed-point arithmetic due to expected power and area savings over ﬂoating-point computation. However, recent research shows that ﬂoating-point arithmetic can be made competitive by using a reduced-precision format instead of, e.g., IEEE standard single precision, thereby avoiding the algorithm design and implementation difﬁculties associated with ﬁxed-point arithmetic. This paper investigates the effects of simpliﬁed ﬂoating-point arithmetic applied to an FMA-based ﬂoating-point unit and the associated software division and square root operations. Software operations are proposed which attain near-exact precision with twice the performance of exact algorithms and resolve overﬂow-related errors with inexpensive exponent-manipulation special instructions.",

author = "Timo Viitanen and Pekka J{\"a}{\"a}skel{\"a}inen and Otto Esko and Jarmo Takala",

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series = "IEEE International Conference on Acoustics, Speech, and Signal Processing",

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Viitanen, T, Jääskeläinen, P, Esko, O & Takala, J 2013, Simplified Floating-Point Division and Square Root. in IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2013, Vancouver, Canada, May 26-31, 2013. IEEE International Conference on Acoustics, Speech, and Signal Processing, IEEE, Piscataway, NJ, pp. 2707-2711, IEEE International Conference on Acoustics, Speech and Signal Processing, 1/01/00. <http://www.icassp2013.com/>

Simplified Floating-Point Division and Square Root. / Viitanen, Timo; Jääskeläinen, Pekka; Esko, Otto et al.
IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2013, Vancouver, Canada, May 26-31, 2013. Piscataway, NJ: IEEE, 2013. p. 2707-2711 (IEEE International Conference on Acoustics, Speech, and Signal Processing).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

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T1 - Simplified Floating-Point Division and Square Root

AU - Viitanen, Timo

AU - Jääskeläinen, Pekka

AU - Esko, Otto

AU - Takala, Jarmo

N1 - Artikkelin post-print-versio saatavilla TUT DPubissa Contribution: organisation=tie,FACT1=1 Portfolio EDEND: 2013-07-29 Publisher name: Institute of Electrical and Electronics Engineers

PY - 2013

Y1 - 2013

N2 - Digital Signal Processing (DSP) algorithms on low-power embedded platforms are often implemented using ﬁxed-point arithmetic due to expected power and area savings over ﬂoating-point computation. However, recent research shows that ﬂoating-point arithmetic can be made competitive by using a reduced-precision format instead of, e.g., IEEE standard single precision, thereby avoiding the algorithm design and implementation difﬁculties associated with ﬁxed-point arithmetic. This paper investigates the effects of simpliﬁed ﬂoating-point arithmetic applied to an FMA-based ﬂoating-point unit and the associated software division and square root operations. Software operations are proposed which attain near-exact precision with twice the performance of exact algorithms and resolve overﬂow-related errors with inexpensive exponent-manipulation special instructions.

AB - Digital Signal Processing (DSP) algorithms on low-power embedded platforms are often implemented using ﬁxed-point arithmetic due to expected power and area savings over ﬂoating-point computation. However, recent research shows that ﬂoating-point arithmetic can be made competitive by using a reduced-precision format instead of, e.g., IEEE standard single precision, thereby avoiding the algorithm design and implementation difﬁculties associated with ﬁxed-point arithmetic. This paper investigates the effects of simpliﬁed ﬂoating-point arithmetic applied to an FMA-based ﬂoating-point unit and the associated software division and square root operations. Software operations are proposed which attain near-exact precision with twice the performance of exact algorithms and resolve overﬂow-related errors with inexpensive exponent-manipulation special instructions.

M3 - Conference contribution

SN - 978-1-4799-0356-6

T3 - IEEE International Conference on Acoustics, Speech, and Signal Processing

SP - 2707

EP - 2711

BT - IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2013, Vancouver, Canada, May 26-31, 2013

PB - IEEE

CY - Piscataway, NJ

T2 - IEEE International Conference on Acoustics, Speech and Signal Processing

Y2 - 1 January 1900 through 1 January 2000

ER -

Simplified Floating-Point Division and Square Root

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