TY - GEN
T1 - Sub-band Digital Predistortion for Noncontiguous Transmissions
T2 - Asilomar Conference on Signals, Systems and Computers
AU - Abdelaziz, Mahmoud
AU - Tarver, Chance
AU - Li, Kaipeng
AU - Anttila, Lauri
AU - Martinez, Raul
AU - Valkama, Mikko
AU - Cavallaro, Joseph R
PY - 2016/2
Y1 - 2016/2
N2 - This article proposes a novel, reduced complexity, block-adaptive digital predistortion (DPD) technique for mitigating the spurious emissions that occur when amplifying spectrally noncontiguous signals with a nonlinear power amplifier (PA). The introduced DPD solution is designed for real-time scenarios where a loop delay exists in the DPD system. By a proper choice of the DPD parameters, the technique is shown to be robust against arbitrarily long loop delays while not sacrificing DPD linearization performance and convergence speed. Moreover, the proposed DPD solution has lower complexity compared to previously proposed solutions in the literature while giving excellent linearization performance in terms of mitigating the spurious emissions. Real-time implementations of the algorithm on the WARP platform are developed, including considerations for several key trade-offs in the hardware design to balance the robustness, performance and complexity. The simulations and real-time FPGA experiments evidence excellent and robust performance in real-life situations with highly nonlinear PAs and arbitrary loop delays.
AB - This article proposes a novel, reduced complexity, block-adaptive digital predistortion (DPD) technique for mitigating the spurious emissions that occur when amplifying spectrally noncontiguous signals with a nonlinear power amplifier (PA). The introduced DPD solution is designed for real-time scenarios where a loop delay exists in the DPD system. By a proper choice of the DPD parameters, the technique is shown to be robust against arbitrarily long loop delays while not sacrificing DPD linearization performance and convergence speed. Moreover, the proposed DPD solution has lower complexity compared to previously proposed solutions in the literature while giving excellent linearization performance in terms of mitigating the spurious emissions. Real-time implementations of the algorithm on the WARP platform are developed, including considerations for several key trade-offs in the hardware design to balance the robustness, performance and complexity. The simulations and real-time FPGA experiments evidence excellent and robust performance in real-life situations with highly nonlinear PAs and arbitrary loop delays.
U2 - 10.1109/ACSSC.2015.7421326
DO - 10.1109/ACSSC.2015.7421326
M3 - Conference contribution
BT - 2015 49th Asilomar Conference on Signals, Systems and Computers
PB - IEEE
Y2 - 1 January 1900
ER -