Three-Level Optimized Pulse Patterns With Bounded Junction Temperature and Relaxed Properties

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Abstract

This paper proposes the computation of three-level optimized pulse patterns (OPPs) that ensure the safe operation of the semiconductor devices, thereby enabling the full utilization of the converter capabilities. To achieve this, the junction temperature of the semiconductor devices is directly bounded in the proposed OPP optimization problem. Additionally, the symmetry properties of the OPPs are relaxed, and multipolar switch positions are allowed to facilitate the redistribution of the thermal stress among the semiconductor devices. This way, the junction temperature requirements can be met without significantly deteriorating the output current ripple. Nevertheless, computing OPPs with relaxed properties can be computationally challenging. To address this, a computationally efficient method based on the concept of virtual angles is employed to render the computation of such OPPs possible. The presented numerical results for medium-voltage drives, consisting of a neutral-point-clamped (NPC) converter and either an induction machine or an externally excited synchronous machine, demonstrate the benefits of the proposed approach.

Original languageEnglish
JournalIEEE Transactions on Power Electronics
DOIs
Publication statusE-pub ahead of print - 30 Oct 2025
Publication typeA1 Journal article-refereed

Keywords

  • Multilevel converters
  • optimal modulation
  • power losses
  • pulse width modulation (PWM)
  • reliability
  • thermal stress

Publication forum classification

  • Publication forum level 3

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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