Towards Benchmarking GNSS Algorithms on FPGA using SyDR

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Global Navigation Satellite System (GNSS) is widely used today for both positioning and timing purposes. Many distinct receiver chips are available off-the-shelf, each tailored to match various applications’ requirements. Being implemented as Application-Specific Integrated Circuits, these chips provide good performance and low energy consumption but must be treated as "black boxes" by customers. This prevents modification, research in GNSS processing chain enhancement (e.g., application of Approximate Computing techniques), and design-space exploration for finding the optimal receiver implementation per each use case. In this paper, we review the development of SyDR, an open-source Software-Defined Radio oriented towards benchmarking of GNSS algorithms. Specifically, our goal is to integrate certain components of the GNSS processing chain in a Field-Programmable Gate Array and manage their operation with a Python program using the Xilinx PYNQ flow. We present the early steps of converting parts of SyDR to C, which will be later converted to Hardware Description Language descriptions using High-Level Synthesis. We demonstrate successful conversion of the tracking process and discuss benefits and drawbacks arising thereof, before outlining next steps in preparation for hardware implementation.
Original languageEnglish
Title of host publication2023 International Conference on Localization and GNSS, ICL-GNSS 2023 - Proceedings
ISBN (Electronic)979-8-3503-2308-5
Publication statusPublished - 14 Jun 2023
Publication typeA4 Article in conference proceedings
EventInternational Conference on Localization and GNSS - Castellón, Spain
Duration: 6 Jun 20238 Jun 2023

Publication series

NameInternational Conference on Localization and GNSS
ISSN (Electronic)2325-0771


ConferenceInternational Conference on Localization and GNSS

Publication forum classification

  • Publication forum level 1


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