Transport Triggered Polar Decoders

Mathieu  Léonardon; Camille Leroux; Pekka Jääskeläinen; Christophe Jego; Yvon Savaria

doi:10.1109/ISTC.2018.8625310

Transport Triggered Polar Decoders

Mathieu Léonardon, Camille Leroux, Pekka Jääskeläinen, Christophe Jego, Yvon Savaria

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

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Abstract

In this paper, the first transport triggered architecture (TTA) customized for the decoding of polar codes is proposed. A first version of this programmable processor is optimized for the successive cancellation (SC) decoding of polar codes while a second architecture is further specialized to also support Soft CANcellation (SCAN) decoding. Both architectures were fully validated on FPGA device by prototyping. The first architecture was also synthesized in 28nm ASIC technology. It runs at a frequency of 800 MHz and reaches a throughput of 352 Mbps for a (1024, 512) polar code decoded with the SC algorithm. Compared to previous work, the energy consumption is reduced by one order of magnitude (0.14 nJ / bit) and the throughput is increased fivefold. Compared to an optimized software implementation on a general purpose processor (x86 architecture), the throughput is 37 % higher and the energy consumption is two orders of magnitude lower. TTA can be seen as a way to reduce the gap between programmable and dedicated polar decoders.

Original language	English
Title of host publication	2018 IEEE 10th International Symposium on Turbo Codes & Iterative Information Processing (ISTC)
Publisher	IEEE
ISBN (Electronic)	978-1-5386-7048-4
DOIs	https://doi.org/10.1109/ISTC.2018.8625310
Publication status	Published - 4 Dec 2018
Publication type	A4 Article in conference proceedings
Event	International Symposium on Turbo Codes & Iterative Information Processing - Hong Kong, China Duration: 3 Dec 2018 → 7 Dec 2018 http://www.istc2018.org/

Conference

Conference	International Symposium on Turbo Codes & Iterative Information Processing
Abbreviated title	ISTC 2018
Country/Territory	China
City	Hong Kong
Period	3/12/18 → 7/12/18
Internet address	http://www.istc2018.org/

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10.1109/ISTC.2018.8625310

Transport Triggered Polar Decoders 2018
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Accepted author manuscript, 335 KB

http://urn.fi/URN:NBN:fi:tuni-202012018355

Cite this

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title = "Transport Triggered Polar Decoders",

abstract = "In this paper, the first transport triggered architecture (TTA) customized for the decoding of polar codes is proposed. A first version of this programmable processor is optimized for the successive cancellation (SC) decoding of polar codes while a second architecture is further specialized to also support Soft CANcellation (SCAN) decoding. Both architectures were fully validated on FPGA device by prototyping. The first architecture was also synthesized in 28nm ASIC technology. It runs at a frequency of 800 MHz and reaches a throughput of 352 Mbps for a (1024, 512) polar code decoded with the SC algorithm. Compared to previous work, the energy consumption is reduced by one order of magnitude (0.14 nJ / bit) and the throughput is increased fivefold. Compared to an optimized software implementation on a general purpose processor (x86 architecture), the throughput is 37 % higher and the energy consumption is two orders of magnitude lower. TTA can be seen as a way to reduce the gap between programmable and dedicated polar decoders.",

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T1 - Transport Triggered Polar Decoders

AU - Léonardon, Mathieu

AU - Leroux, Camille

AU - Jääskeläinen, Pekka

AU - Jego, Christophe

AU - Savaria, Yvon

PY - 2018/12/4

Y1 - 2018/12/4

N2 - In this paper, the first transport triggered architecture (TTA) customized for the decoding of polar codes is proposed. A first version of this programmable processor is optimized for the successive cancellation (SC) decoding of polar codes while a second architecture is further specialized to also support Soft CANcellation (SCAN) decoding. Both architectures were fully validated on FPGA device by prototyping. The first architecture was also synthesized in 28nm ASIC technology. It runs at a frequency of 800 MHz and reaches a throughput of 352 Mbps for a (1024, 512) polar code decoded with the SC algorithm. Compared to previous work, the energy consumption is reduced by one order of magnitude (0.14 nJ / bit) and the throughput is increased fivefold. Compared to an optimized software implementation on a general purpose processor (x86 architecture), the throughput is 37 % higher and the energy consumption is two orders of magnitude lower. TTA can be seen as a way to reduce the gap between programmable and dedicated polar decoders.

AB - In this paper, the first transport triggered architecture (TTA) customized for the decoding of polar codes is proposed. A first version of this programmable processor is optimized for the successive cancellation (SC) decoding of polar codes while a second architecture is further specialized to also support Soft CANcellation (SCAN) decoding. Both architectures were fully validated on FPGA device by prototyping. The first architecture was also synthesized in 28nm ASIC technology. It runs at a frequency of 800 MHz and reaches a throughput of 352 Mbps for a (1024, 512) polar code decoded with the SC algorithm. Compared to previous work, the energy consumption is reduced by one order of magnitude (0.14 nJ / bit) and the throughput is increased fivefold. Compared to an optimized software implementation on a general purpose processor (x86 architecture), the throughput is 37 % higher and the energy consumption is two orders of magnitude lower. TTA can be seen as a way to reduce the gap between programmable and dedicated polar decoders.

U2 - 10.1109/ISTC.2018.8625310

DO - 10.1109/ISTC.2018.8625310

M3 - Conference contribution

BT - 2018 IEEE 10th International Symposium on Turbo Codes & Iterative Information Processing (ISTC)

PB - IEEE

T2 - International Symposium on Turbo Codes & Iterative Information Processing

Y2 - 3 December 2018 through 7 December 2018

ER -

Transport Triggered Polar Decoders

Abstract

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