Transport-Triggered Soft Cores

Pekka Jääskeläinen, Aleksi Tervo, Guillermo Paya-Vaya, Timo Viitanen, Nicolai Behmann, Jarmo Takala, Holger Blume

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    18 Citations (Scopus)
    459 Downloads (Pure)

    Abstract

    Soft cores are used as flexible software programmable components in FPGA designs. Transport-Triggered Architecture (TTA) is interesting for this use due to its scalability, modularity, simplified register files (RF) and fine-grained compiler control, but has the drawback of wider instructions and additional multiplexing due to extensive RF port sharing. In this paper we evaluate the trade-offs of TTA in soft core use in comparison to its closest multi-issue relative, the traditional "operation triggered" VLIW architecture, as well as the Xilinx MicroBlaze, a popular single-issue soft core. For the compared alternatives running CHStone benchmarks, the dual-issue TTA with a monolithic RF provides the best performance/area trade-off. Its program size increase varies from 21% to 49% in comparison to the VLIW programming model. However, synthesis results on a Xilinx Zynq Z7020 device show that the dual-issue TTA requires 67% of the resources while providing up to 88% improvement in execution time compared to VLIW. Partitioning the RF is found beneficial for both VLIW and TTA programming models, resulting in a very similar FPGA resource usage, but with TTA model improving execution time up to 77%. As a single-issue soft core, we measured execution time improvements up to 173% when comparing with the TTA approach against the performance-optimized MicroBlaze with similar datapath resources.
    Original languageEnglish
    Title of host publication 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
    PublisherIEEE
    ISBN (Electronic)978-1-5386-5555-9
    DOIs
    Publication statusPublished - 21 May 2018
    Publication typeA4 Article in conference proceedings
    EventReconfigurable Architectures Workshop - 32nd Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2018) , Vancouver, Canada
    Duration: 21 May 201822 May 2018
    Conference number: 25
    http://raw.necst.it/

    Conference

    ConferenceReconfigurable Architectures Workshop
    Abbreviated titleRAW
    Country/TerritoryCanada
    CityVancouver
    Period21/05/1822/05/18
    Internet address

    Publication forum classification

    • Publication forum level 1

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