TY - GEN
T1 - Using Modified Bessel Functions For Calculations of Drain Current Harmonics In a MOS Transistor Operating in Moderate Inversion
AU - Filanovsky, Igor
AU - Oliveira, Luis
AU - Tchamov, Nikolay
N1 - jufoid=86927
PY - 2018/5/27
Y1 - 2018/5/27
N2 - The paper describes evaluation of drain current harmonics in a MOS transistor operating in moderate inversion and strong saturation. The dependence of the drain current on the gate-source and drain-source voltages is described using a simplified 'reconciliation' model developed by Y. Tsividis. Then, in the proposed model the current components corresponding to the terms depending exponentially on normalized gate-source and/or drain-source modulating sinusoidal voltage are evaluated using modified Bessel functions. This approach allows one to omit the small-signal requirement for modulating signals, and calculate the first, second and third harmonics of the drain current caused by the gate-source or drain-source voltages and also find the intermodulation terms. The results are applied to the design of low-distortion low-voltage amplifiers. The recommendations are confirmed by simulations.
AB - The paper describes evaluation of drain current harmonics in a MOS transistor operating in moderate inversion and strong saturation. The dependence of the drain current on the gate-source and drain-source voltages is described using a simplified 'reconciliation' model developed by Y. Tsividis. Then, in the proposed model the current components corresponding to the terms depending exponentially on normalized gate-source and/or drain-source modulating sinusoidal voltage are evaluated using modified Bessel functions. This approach allows one to omit the small-signal requirement for modulating signals, and calculate the first, second and third harmonics of the drain current caused by the gate-source or drain-source voltages and also find the intermodulation terms. The results are applied to the design of low-distortion low-voltage amplifiers. The recommendations are confirmed by simulations.
KW - MOS transistor model, moderate inversion,
U2 - 10.1109/ISCAS.2018.8350949
DO - 10.1109/ISCAS.2018.8350949
M3 - Conference contribution
BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
PB - IEEE
T2 - IEEE International Symposium on Circuits and Systems
Y2 - 27 May 2018 through 30 May 2018
ER -