TY - GEN
T1 - Variable Time-Step 2.5-15 GHz Phase Modulator with Pre-Distortion for Outphasing Transmitters
AU - Cheung, Tze Hin
AU - Ghosh, Agnimesh
AU - Spelman, Andrei
AU - Boopathy, Dhanashree
AU - Unnikrishnan, Vishnu
AU - Anttila, Lauri
AU - Valkama, Mikko
AU - Kosunen, Marko
AU - Stadius, Kari
AU - Ryynänen, Jussi
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Radio transmitters for 5G and beyond communication employ high signal bandwidths and carrier frequencies, setting stringent requirements on the design of transceiver circuits in terms of timing and complexity. Phase modulators act as information encoders as well as delay lines for accurate timing compensation circuits. In this paper we present a configurable variable time-step 2.5-15 GHz 7-bit phase modulator with non-linearity pre-distortion and calibration capabilities. The proposed design exhibits highly linear operation and uses mixed-mode design approach with analog phase modulator and digital binary-to-unary unit for calibration and predistortion. The proposed design is implemented in 22-nm CMOS and occupies 0.68 mm2 die area. Simulations across process-voltage-temperature variations indicate consistent dynamic non-linearity (DNL) performance. The design reaches a worst-case DNL performance of 0.43 LSB (least-significant-bit) at 15 GHz operating frequency.
AB - Radio transmitters for 5G and beyond communication employ high signal bandwidths and carrier frequencies, setting stringent requirements on the design of transceiver circuits in terms of timing and complexity. Phase modulators act as information encoders as well as delay lines for accurate timing compensation circuits. In this paper we present a configurable variable time-step 2.5-15 GHz 7-bit phase modulator with non-linearity pre-distortion and calibration capabilities. The proposed design exhibits highly linear operation and uses mixed-mode design approach with analog phase modulator and digital binary-to-unary unit for calibration and predistortion. The proposed design is implemented in 22-nm CMOS and occupies 0.68 mm2 die area. Simulations across process-voltage-temperature variations indicate consistent dynamic non-linearity (DNL) performance. The design reaches a worst-case DNL performance of 0.43 LSB (least-significant-bit) at 15 GHz operating frequency.
U2 - 10.1109/NewCAS58973.2024.10666306
DO - 10.1109/NewCAS58973.2024.10666306
M3 - Conference contribution
AN - SCOPUS:85205698422
T3 - 2024 22nd IEEE Interregional NEWCAS Conference, NEWCAS 2024
SP - 288
EP - 292
BT - 2024 22nd IEEE Interregional NEWCAS Conference, NEWCAS 2024
PB - IEEE
T2 - IEEE Interregional NEWCAS Conference
Y2 - 16 June 2024 through 19 June 2024
ER -