Visualization of memory map information in embedded system design

Mikko Teuho; Esko Pekkarinen; Timo D. Hämäläinen

doi:10.1109/DSD.2018.00040

Visualization of memory map information in embedded system design

Mikko Teuho, Esko Pekkarinen, Timo D. Hämäläinen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

Abstract

Data compression is a common requirement for displaying large amounts of information. The goal is to reduce visual clutter. The approach given in this paper uses an analysis of a data set to construct a visual representation. The visualization is compressed using the address ranges of the memory structure. This method produces a compressed version of the initial visualization, retaining the same information as the original. The presented method has been implemented as a Memory Designer tool for ASIC, FPGA and embedded systems using IP-XACT. The Memory Designer is a user-friendly tool for model based embedded system design, providing access and adjustment of the memory layout from a single view, complementing the 'programmer's view' to the system.

Original language	English
Title of host publication	Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018
Publisher	IEEE
Pages	163-166
Number of pages	4
ISBN (Electronic)	9781538673768
DOIs	https://doi.org/10.1109/DSD.2018.00040
Publication status	Published - 12 Oct 2018
Publication type	A4 Article in a conference publication
Event	Euromicro Conference on Digital System Design - Prague, Czech Republic Duration: 29 Aug 2018 → 31 Aug 2018

Conference

Conference	Euromicro Conference on Digital System Design
Country/Territory	Czech Republic
City	Prague
Period	29/08/18 → 31/08/18

Keywords

Compression
Data visualization
Display space
Filtering
Memory structure

Publication forum classification

Publication forum level 1

ASJC Scopus subject areas

Hardware and Architecture

Access to Document

10.1109/DSD.2018.00040

Cite this

@inproceedings{678dffd41aad4a3ba608d9b7c75bd650,

title = "Visualization of memory map information in embedded system design",

abstract = "Data compression is a common requirement for displaying large amounts of information. The goal is to reduce visual clutter. The approach given in this paper uses an analysis of a data set to construct a visual representation. The visualization is compressed using the address ranges of the memory structure. This method produces a compressed version of the initial visualization, retaining the same information as the original. The presented method has been implemented as a Memory Designer tool for ASIC, FPGA and embedded systems using IP-XACT. The Memory Designer is a user-friendly tool for model based embedded system design, providing access and adjustment of the memory layout from a single view, complementing the 'programmer's view' to the system.",

keywords = "Compression, Data visualization, Display space, Filtering, Memory structure",

author = "Mikko Teuho and Esko Pekkarinen and H{\"a}m{\"a}l{\"a}inen, {Timo D.}",

year = "2018",

month = oct,

day = "12",

doi = "10.1109/DSD.2018.00040",

language = "English",

pages = "163--166",

booktitle = "Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018",

publisher = "IEEE",

note = "Euromicro Conference on Digital System Design ; Conference date: 29-08-2018 Through 31-08-2018",

}

TY - GEN

T1 - Visualization of memory map information in embedded system design

AU - Teuho, Mikko

AU - Pekkarinen, Esko

AU - Hämäläinen, Timo D.

PY - 2018/10/12

Y1 - 2018/10/12

N2 - Data compression is a common requirement for displaying large amounts of information. The goal is to reduce visual clutter. The approach given in this paper uses an analysis of a data set to construct a visual representation. The visualization is compressed using the address ranges of the memory structure. This method produces a compressed version of the initial visualization, retaining the same information as the original. The presented method has been implemented as a Memory Designer tool for ASIC, FPGA and embedded systems using IP-XACT. The Memory Designer is a user-friendly tool for model based embedded system design, providing access and adjustment of the memory layout from a single view, complementing the 'programmer's view' to the system.

AB - Data compression is a common requirement for displaying large amounts of information. The goal is to reduce visual clutter. The approach given in this paper uses an analysis of a data set to construct a visual representation. The visualization is compressed using the address ranges of the memory structure. This method produces a compressed version of the initial visualization, retaining the same information as the original. The presented method has been implemented as a Memory Designer tool for ASIC, FPGA and embedded systems using IP-XACT. The Memory Designer is a user-friendly tool for model based embedded system design, providing access and adjustment of the memory layout from a single view, complementing the 'programmer's view' to the system.

KW - Compression

KW - Data visualization

KW - Display space

KW - Filtering

KW - Memory structure

U2 - 10.1109/DSD.2018.00040

DO - 10.1109/DSD.2018.00040

M3 - Conference contribution

AN - SCOPUS:85056487173

SP - 163

EP - 166

BT - Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018

PB - IEEE

T2 - Euromicro Conference on Digital System Design

Y2 - 29 August 2018 through 31 August 2018

ER -

Visualization of memory map information in embedded system design

Abstract

Conference

Keywords

Publication forum classification

ASJC Scopus subject areas

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Cite this