VLSI Architecture of Arithmetic Coder Used in SPIHT

Kai Liu; Evgeniy Belyaev; Jie Guo

doi:10.1109/TVLSI.2011.2109068

VLSI Architecture of Arithmetic Coder Used in SPIHT

Kai Liu
, Evgeniy Belyaev
, Jie Guo

Research output: Contribution to journal › Article › Scientific › peer-review

15 Citations (Scopus)

Translated title of the contribution	VLSI Architecture of Arithmetic Coder Used in SPIHT
Original language	English
Pages (from-to)	697-710
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	20
Issue number	4
DOIs	https://doi.org/10.1109/TVLSI.2011.2109068
Publication status	Published - 2012
Externally published	Yes
Publication type	A1 Journal article-refereed

Publication forum classification

Publication forum level 2

Access to Document

10.1109/TVLSI.2011.2109068

Cite this

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title = "VLSI Architecture of Arithmetic Coder Used in SPIHT",

author = "Kai Liu and Evgeniy Belyaev and Jie Guo",

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journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

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AU - Liu, Kai

AU - Belyaev, Evgeniy

AU - Guo, Jie

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DO - 10.1109/TVLSI.2011.2109068

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JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 4

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