Abstrakti
Networking devices such as switches and routers have traditionally had fixed functionality. They have the logic for the union of network protocols matching the application and market segment for which they have been designed. Possibility of adding new functionality is limited. One of the aims of Software Defined Networking is to make packet processing devices programmable. This provides for innovation and rapid deployment of novel networking protocols. The first step in processing of packets is packet parsing. In this paper, we present a custom processor for packet parsing. The parser is protocol-independent and can be programmed to parse any sequence of headers. It does so without the use of a Ternary Content Addressable Memory. As a result, the area and power consumption are noticeably smaller than in the state of the art. Moreover, its output is the same as that of the parser used in the Reconfigurable Match Tables (RMT). With an area no more than that of parsers in the RMT architecture, it sustains aggregate throughput of 3.4 Tbps in the worst case which is an improvement by a factor of 5.
| Alkuperäiskieli | Englanti |
|---|---|
| Sivumäärä | 11 |
| Julkaisu | Microprocessors and Microsystems |
| Vuosikerta | 72 |
| Varhainen verkossa julkaisun päivämäärä | 2019 |
| DOI - pysyväislinkit | |
| Tila | Julkaistu - 1 helmik. 2020 |
| OKM-julkaisutyyppi | A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä |
Rahoitus
We hereby express our gratitude to professor Nick McKeown from Stanford University for providing us with the details on the area of the parser used in [6] . We would also like to thank Mr. Glen Gibb for providing us with invaluable comments and insight. We acknowledge the Finnish DELTA network and The Pekka Ahonen Fund for providing partial funding for this project. Hesam Zolfaghari is a doctoral student at Tampere University. His-research interest is design of programmable and protocol-independent packet processors for Software Defined Networking with special focuses on low on-chip area, low power dissipation and minimized packet processing latency. This includes design of abstraction layers starting from the instruction set all the way down to the microarchitecture of both packet parsing and packet processing subsystems within high-performance switches and routers. Davide Rossi , received the PhD from the University of Bologna, Italy, in 2012. He has been a post doc researcher in the Department of Electrical, Electronic and Information Engineering “Guglielmo Marconi” at the University of Bologna since 2015, where he currently holds an assistant professor position. His research interests focus on energy efficient digital architectures in the domain of heterogeneous and reconfigurable multi and many-core systems on a chip. In these fields he has published more than 80 paper in international peer-reviewed conferences and journals. D. Sc. (Tech) Jari Nurmi is Professor at Tampere University (formerly Tampere University of Technology), Finland since 1999. He works on embedded computing, wireless localization, and software-defined radio/networks. He held various positions at TUT 1987–1994 and was the Vice President of SME VLSI Solution Oy 1995–1998. Since 2013 he is also a partner at research spin-offs. He has supervised 25 PhD and 138 MSc theses, and been opponent/reviewer of 40 PhD theses worldwide. He is senior member of IEEE, and in steering committees of three international conferences (chairman in two). He has edited five Springer books, and published over 350 international publications.
Julkaisufoorumi-taso
- Jufo-taso 1
!!ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Computer Networks and Communications
- Artificial Intelligence
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