A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck

C. Brunelli; F. Garzia; C. Giliberto; J. Nurmi

doi:10.1109/FPL.2008.4629990

A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck

Julkaisun otsikon käännös: A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck

C. Brunelli, F. Garzia, C. Giliberto, J. Nurmi

Tutkimustuotos: Konferenssiartikkeli › Tieteellinen › vertaisarvioitu

21 Sitaatiot (Scopus)

Julkaisun otsikon käännös	A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck
Alkuperäiskieli	Englanti
Otsikko	Proceedings of 2008 International Conference on Field Programmable Logic and Applications FPL, 8-10 September, 2008, Heidelberg, Germany
Toimittajat	U. Kebschull, M. Platzner, J. Teich
Sivut	487-490
DOI - pysyväislinkit	https://doi.org/10.1109/FPL.2008.4629990
Tila	Julkaistu - 2008
OKM-julkaisutyyppi	A4 Artikkeli konferenssijulkaisussa

Julkaisufoorumi-taso

Ei tasoa

Pääsy asiakirjaan

10.1109/FPL.2008.4629990

Siteeraa tätä

Brunelli, C., Garzia, F., Giliberto, C., & Nurmi, J. (2008). A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck. teoksessa U. Kebschull, M. Platzner, & J. Teich (Toimittajat), Proceedings of 2008 International Conference on Field Programmable Logic and Applications FPL, 8-10 September, 2008, Heidelberg, Germany (Sivut 487-490) https://doi.org/10.1109/FPL.2008.4629990

Brunelli, C. ; Garzia, F. ; Giliberto, C. et al. / A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck. Proceedings of 2008 International Conference on Field Programmable Logic and Applications FPL, 8-10 September, 2008, Heidelberg, Germany. Toimittaja / U. Kebschull ; M. Platzner ; J. Teich. 2008. Sivut 487-490

@inproceedings{c722ff45287743bf8342fa968a034331,

title = "A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck",

author = "C. Brunelli and F. Garzia and C. Giliberto and J. Nurmi",

note = "Contribution: organisation=tkt,FACT1=1",

year = "2008",

doi = "10.1109/FPL.2008.4629990",

language = "English",

isbn = "978-1-4244-1961-6",

pages = "487--490",

editor = "U. Kebschull and M. Platzner and J. Teich",

booktitle = "Proceedings of 2008 International Conference on Field Programmable Logic and Applications FPL, 8-10 September, 2008, Heidelberg, Germany",

}

Brunelli, C, Garzia, F, Giliberto, C & Nurmi, J 2008, A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck. julkaisussa U Kebschull, M Platzner & J Teich (toim), Proceedings of 2008 International Conference on Field Programmable Logic and Applications FPL, 8-10 September, 2008, Heidelberg, Germany. Sivut 487-490. https://doi.org/10.1109/FPL.2008.4629990

A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck. / Brunelli, C.; Garzia, F.; Giliberto, C. et al.
Proceedings of 2008 International Conference on Field Programmable Logic and Applications FPL, 8-10 September, 2008, Heidelberg, Germany. toim. / U. Kebschull; M. Platzner; J. Teich. 2008. s. 487-490.

Tutkimustuotos: Konferenssiartikkeli › Tieteellinen › vertaisarvioitu

TY - GEN

T1 - A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck

AU - Brunelli, C.

AU - Garzia, F.

AU - Giliberto, C.

AU - Nurmi, J.

N1 - Contribution: organisation=tkt,FACT1=1

PY - 2008

Y1 - 2008

U2 - 10.1109/FPL.2008.4629990

DO - 10.1109/FPL.2008.4629990

M3 - Conference contribution

SN - 978-1-4244-1961-6

SP - 487

EP - 490

BT - Proceedings of 2008 International Conference on Field Programmable Logic and Applications FPL, 8-10 September, 2008, Heidelberg, Germany

A2 - Kebschull, U.

A2 - Platzner, M.

A2 - Teich, J.

ER -

Brunelli C, Garzia F, Giliberto C, Nurmi J. A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck. julkaisussa Kebschull U, Platzner M, Teich J, toimittajat, Proceedings of 2008 International Conference on Field Programmable Logic and Applications FPL, 8-10 September, 2008, Heidelberg, Germany. 2008. s. 487-490 doi: 10.1109/FPL.2008.4629990