A low-power fractional decimator architecture for an IF-sampling dual-mode receiver

Julkaisun otsikon käännös: A low-power fractional decimator architecture for an IF-sampling dual-mode receiver

Tutkimustuotos: Konferenssiartikkeli › Tieteellinen › vertaisarvioitu

Julkaisun otsikon käännös	A low-power fractional decimator architecture for an IF-sampling dual-mode receiver
Alkuperäiskieli	Englanti
Otsikko	Proceedings of 2004 IEEE International Symposium on Circuits and Systems, 23-26, May, 2004, Vancouver, British Columbia, Canada
Sivut	589-592
Tila	Julkaistu - 2004
OKM-julkaisutyyppi	A4 Artikkeli konferenssijulkaisussa

Julkaisufoorumi-taso

@inproceedings{c3a7618f7b89472c8f34837207e90d1d,

title = "A low-power fractional decimator architecture for an IF-sampling dual-mode receiver",

author = "R. Uusikartano and J. Takala",

note = "ISBN 0-7803-8252-8<br/>Contribution: organisation=tkt,FACT1=1",

year = "2004",

language = "English",

pages = "589--592",

booktitle = "Proceedings of 2004 IEEE International Symposium on Circuits and Systems, 23-26, May, 2004, Vancouver, British Columbia, Canada",

}

TY - GEN

T1 - A low-power fractional decimator architecture for an IF-sampling dual-mode receiver

AU - Uusikartano, R.

AU - Takala, J.

N1 - ISBN 0-7803-8252-8<br/>Contribution: organisation=tkt,FACT1=1

PY - 2004

Y1 - 2004

M3 - Conference contribution

SP - 589

EP - 592

BT - Proceedings of 2004 IEEE International Symposium on Circuits and Systems, 23-26, May, 2004, Vancouver, British Columbia, Canada

ER -