A RTL asynchronous FIFO design using modified micropipeline

Xin Wang; Jari Nurmi

doi:10.1109/BEC.2006.311069

A RTL asynchronous FIFO design using modified micropipeline

Xin Wang, Jari Nurmi

Tutkimustuotos: Konferenssiartikkeli › Tieteellinen › vertaisarvioitu

9 Sitaatiot (Scopus)

Abstrakti

An asynchronous FIFO which applies fourphase handshake protocol to read or write data has been designed in Register-Transfer Level (RTL) using VHDL. The asynchronous FIFO in this paper avoids data movement in a flow-through FIFO by applying token passing scheme in its control pipelines and multiplexer in its data register bank. Two control pipelines which base on micropipeline structure are proposed and used as the control logic for the asynchronous FIFO. An asynchronous arbiter and C-element RTL structures used in the proposed asynchronous FIFO are also presented.

Alkuperäiskieli	Englanti
Otsikko	BEC 2006 - 2006 International Baltic Electronics Conference; Proceedings of the 10th Biennial Baltic Electronics Conference
Sivut	95-98
Sivumäärä	4
DOI - pysyväislinkit	https://doi.org/10.1109/BEC.2006.311069
Tila	Julkaistu - 2006
OKM-julkaisutyyppi	A4 Artikkeli konferenssijulkaisussa
Tapahtuma	BEC 2006 - 2006 International Baltic Electronics Conference; 10th Biennial Batic Electronics Conference - Tallinn, Viro Kesto: 2 lokak. 2006 → 4 lokak. 2006

Conference

Conference	BEC 2006 - 2006 International Baltic Electronics Conference; 10th Biennial Batic Electronics Conference
Maa/Alue	Viro
Kaupunki	Tallinn
Ajanjakso	2/10/06 → 4/10/06

!!ASJC Scopus subject areas

Electrical and Electronic Engineering

Pääsy asiakirjaan

10.1109/BEC.2006.311069

Siteeraa tätä

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title = "A RTL asynchronous FIFO design using modified micropipeline",

abstract = "An asynchronous FIFO which applies fourphase handshake protocol to read or write data has been designed in Register-Transfer Level (RTL) using VHDL. The asynchronous FIFO in this paper avoids data movement in a flow-through FIFO by applying token passing scheme in its control pipelines and multiplexer in its data register bank. Two control pipelines which base on micropipeline structure are proposed and used as the control logic for the asynchronous FIFO. An asynchronous arbiter and C-element RTL structures used in the proposed asynchronous FIFO are also presented.",

author = "Xin Wang and Jari Nurmi",

year = "2006",

doi = "10.1109/BEC.2006.311069",

language = "English",

isbn = "1424404150",

pages = "95--98",

booktitle = "BEC 2006 - 2006 International Baltic Electronics Conference; Proceedings of the 10th Biennial Baltic Electronics Conference",

note = "BEC 2006 - 2006 International Baltic Electronics Conference; 10th Biennial Batic Electronics Conference ; Conference date: 02-10-2006 Through 04-10-2006",

}

Wang, X & Nurmi, J 2006, A RTL asynchronous FIFO design using modified micropipeline. julkaisussa BEC 2006 - 2006 International Baltic Electronics Conference; Proceedings of the 10th Biennial Baltic Electronics Conference. Sivut 95-98, BEC 2006 - 2006 International Baltic Electronics Conference; 10th Biennial Batic Electronics Conference, Tallinn, Viro, 2/10/06. https://doi.org/10.1109/BEC.2006.311069

TY - GEN

T1 - A RTL asynchronous FIFO design using modified micropipeline

AU - Wang, Xin

AU - Nurmi, Jari

PY - 2006

Y1 - 2006

N2 - An asynchronous FIFO which applies fourphase handshake protocol to read or write data has been designed in Register-Transfer Level (RTL) using VHDL. The asynchronous FIFO in this paper avoids data movement in a flow-through FIFO by applying token passing scheme in its control pipelines and multiplexer in its data register bank. Two control pipelines which base on micropipeline structure are proposed and used as the control logic for the asynchronous FIFO. An asynchronous arbiter and C-element RTL structures used in the proposed asynchronous FIFO are also presented.

AB - An asynchronous FIFO which applies fourphase handshake protocol to read or write data has been designed in Register-Transfer Level (RTL) using VHDL. The asynchronous FIFO in this paper avoids data movement in a flow-through FIFO by applying token passing scheme in its control pipelines and multiplexer in its data register bank. Two control pipelines which base on micropipeline structure are proposed and used as the control logic for the asynchronous FIFO. An asynchronous arbiter and C-element RTL structures used in the proposed asynchronous FIFO are also presented.

U2 - 10.1109/BEC.2006.311069

DO - 10.1109/BEC.2006.311069

M3 - Conference contribution

AN - SCOPUS:46249126082

SN - 1424404150

SN - 9781424404155

SP - 95

EP - 98

BT - BEC 2006 - 2006 International Baltic Electronics Conference; Proceedings of the 10th Biennial Baltic Electronics Conference

T2 - BEC 2006 - 2006 International Baltic Electronics Conference; 10th Biennial Batic Electronics Conference

Y2 - 2 October 2006 through 4 October 2006

ER -

A RTL asynchronous FIFO design using modified micropipeline

Abstrakti

Conference

!!ASJC Scopus subject areas

Pääsy asiakirjaan

Sormenjälki

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