A simplified executable model to evaluate latency and throughput of networks-on-chip

Julkaisun otsikon käännös: A simplified executable model to evaluate latency and throughput of networks-on-chip

L. Ost, F. G. Moraes, L. Möller, L. Soares Indrusiak, M. Glesner, S. Määttä, J. Nurmi

Tutkimustuotos: Konferenssiartikkeli › Tieteellinen › vertaisarvioitu

11 Sitaatiot (Scopus)

Julkaisun otsikon käännös	A simplified executable model to evaluate latency and throughput of networks-on-chip
Alkuperäiskieli	Englanti
Otsikko	SBCCI 2008, 21st Symposium on Integrated Circuits and Systems Design, Gramado, Brazil, September 1 to 4, 2008
Sivut	170-175
DOI - pysyväislinkit	https://doi.org/10.1145/1404371.1404420
Tila	Julkaistu - 2008
OKM-julkaisutyyppi	A4 Artikkeli konferenssijulkaisussa

Julkaisufoorumi-taso

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title = "A simplified executable model to evaluate latency and throughput of networks-on-chip",

author = "L. Ost and Moraes, {F. G.} and L. M{\"o}ller and {Soares Indrusiak}, L. and M. Glesner and S. M{\"a}{\"a}tt{\"a} and J. Nurmi",

note = "Contribution: organisation=tkt,FACT1=1",

year = "2008",

doi = "10.1145/1404371.1404420",

language = "English",

isbn = "978-1-60558-231-3",

pages = "170--175",

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T1 - A simplified executable model to evaluate latency and throughput of networks-on-chip

AU - Ost, L.

AU - Moraes, F. G.

AU - Möller, L.

AU - Soares Indrusiak, L.

AU - Glesner, M.

AU - Määttä, S.

AU - Nurmi, J.

N1 - Contribution: organisation=tkt,FACT1=1

PY - 2008

Y1 - 2008

U2 - 10.1145/1404371.1404420

DO - 10.1145/1404371.1404420

M3 - Conference contribution

SN - 978-1-60558-231-3

SP - 170

EP - 175

BT - SBCCI 2008, 21st Symposium on Integrated Circuits and Systems Design, Gramado, Brazil, September 1 to 4, 2008

ER -