Design and Evaluation of Correlation Accelerator in IEEE-802.11a/g Receiver using a Template-based Coarse-Grained Reconfigurable Array

This paper presents the design and evaluation of a large scale template-based Coarse-Grained Reconfigurable Array (CGRA) generated accelerator that processes correlation algorithm for Timing Synchronization (TS) required in Orthogonal Frequency-Division Multiplexing (OFDM) receivers. The CGRA works as a coprocessor with a Reduced Instruction-Set Computing (RISC) processor. The CGRA accelerator is composed of 80 reconfigurable Processing Elements (PEs) to compute 80-point correlation in 1.8 μs when synthesized on an Field Programmable Gate Array (FPGA). The power consumption is estimated by simulating the postfit gate-level FPGA netlist of the TS accelerator followed by evaluation and comparison with other state-of-the-art platforms in terms of multiple performance metrics.