Design and verification of a VHDL model of a floating-point unit for a RISC microprocessor

Julkaisun otsikon käännös: Design and verification of a VHDL model of a floating-point unit for a RISC microprocessor

C. Brunelli, J. Nurmi

Tutkimustuotos: Konferenssiartikkeli › Tieteellinen › vertaisarvioitu

Julkaisun otsikon käännös	Design and verification of a VHDL model of a floating-point unit for a RISC microprocessor
Alkuperäiskieli	Englanti
Otsikko	Proceedings of 2006 International Symposium on system-on-Chip, 13-16 November, 2006, Tampere, Finland
Toimittajat	J. Nurmi, J. Takala
Sivut	87-90
Tila	Julkaistu - 2006
OKM-julkaisutyyppi	A4 Artikkeli konferenssijulkaisussa

Julkaisufoorumi-taso

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title = "Design and verification of a VHDL model of a floating-point unit for a RISC microprocessor",

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year = "2006",

language = "English",

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editor = "J. Nurmi and J. Takala",

booktitle = "Proceedings of 2006 International Symposium on system-on-Chip, 13-16 November, 2006, Tampere, Finland",

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AU - Nurmi, J.

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PY - 2006

Y1 - 2006

M3 - Conference contribution

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BT - Proceedings of 2006 International Symposium on system-on-Chip, 13-16 November, 2006, Tampere, Finland

A2 - Nurmi, J.

A2 - Takala, J.

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