Evaluation of the State of High-level Synthesis: A hardware engineer's perspective

Increasing productivity is a constant challenge in the design of applications for field-programmable gate arrays (FPGAs) and application-specific integrated circuits. The complexity of these devices grows at a rate similar to Moore’s law, requiring an equivalent increase in productivity to keep engineering costs manageable. One way to increase productivity is by raising the abstraction level of the designs. By designing from a more abstract entry, electronic design automation tools can plan the lower-level details based on the design entry and technological constraints.

High-level synthesis (HLS) is the most promising candidate for raising the abstraction level for these designs. In HLS, the design entry is given in high-level code, usually in a language originally developed for the software domain. An HLS tool takes this source code input, information on target technology, and architectural details to produce a register-transfer level (RTL) output that can be used with downstream synthesis tools.

Commercial HLS tools have been available for decades, but only started to gain traction in the industry in the last 10-20 years. While it is widely accepted that HLS lowers the design effort significantly, it has been the perception that the quality of results (QoR) in terms of performance and area lags behind those attainable by manual RTL (mRTL) methods.

This thesis studies the current state of HLS for FPGA-based designs. It aims to determine what productivity benefits can be expected from HLS and what the QoR of results is compared to mRTL methods that still dominate the industry. It also surveys the HLS tools available and what features they have. C++, the most popular input language, is given special attention by inspecting how productivity can be increased by adopting the newest C++ standards for HLS. The productivity and QoR of HLS are studied by an extensive literature survey based on articles published during the last ten years. Further insight is attained by three case studies that use HLS to implement applications that demand different design considerations.

The thesis concludes that HLS can be used to accelerate the design process. Development effort reduction of the order of 50 % can be expected compared to mRTL methods. However, achieving high QoR requires HLS-specific expertise from engineers and significant revisions to software-based application models. If the best performance and lowest area are required, mRTL methods still seem the safest choice, assuming that time-to-market is not critical. Otherwise, HLS should be considered.

The thesis also makes recommendations based on the findings for HLS tool developers to increase the productivity and QoR of HLS-based designs.