High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA

    Tutkimustuotos: Conference contributionScientificvertaisarvioitu

    17 Sitaatiot (Scopus)

    Abstrakti

    This paper presents a High-Level Synthesis (HLS) flow for mapping a software HEVC encoder into Altera CycloneV SoC-FPGA. The starting point is a C
    implementation of an open-source Kvazaar HEVC intra encoder, which is minimally refined for SystemC design space exploration and automatic Catapult-C RTL generation. The final implementation involves Kvazaar encoder executed in Linux on dual-core ARM, and HW accelerated intra prediction
    on FPGA. Changing the SW/HW partitioning or modifying the implementation takes hours instead of weeks with Catapult-C HLS. In addition, the design is portable to other platforms without major manual re-writing. We obtained 9 fps full-HD intra prediction speed with a single accelerator on Altera Cyclone V SX on Terasic VEEK-MT-C5SoC board including video capture and HEVC video streaming via Ethernet. To the best of our knowledge, this is the first reported HLS assisted implementation of HEVC encoder on SoC-FPGA.
    AlkuperäiskieliEnglanti
    Otsikko18th Euromicro Conference on Digital Systems Design (DSD 2015)
    KustantajaIEEE
    Sivut49 - 56
    Sivumäärä8
    ISBN (painettu)978-1-4673-8035-5
    DOI - pysyväislinkit
    TilaJulkaistu - 2015
    OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisussa
    TapahtumaEUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN -
    Kesto: 1 tammikuuta 1900 → …

    Conference

    ConferenceEUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN
    Ajanjakso1/01/00 → …

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