High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA

    Tutkimustuotos: Conference contributionScientificvertaisarvioitu

    10 Sitaatiot (Scopus)
    16 Lataukset (Pure)

    Abstrakti

    This paper presents the first known high-level synthesis (HLS) implementation of integer discrete cosine transform (DCT) and discrete sine transform (DST) for High Efficiency Video Coding (HEVC). The proposed approach implements these 2-D transforms by two successive 1-D transforms using a well-known row-column and Even-Odd decomposition techniques. Altogether, the proposed architecture is composed of a 4-point DCT/DST unit for the smallest transform blocks (TBs), an 8/16/32-point DCT unit for the other TBs, and a transpose memory for intermediate results. On Arria II FPGA, the low-cost variant of the proposed architecture is able to support encoding of 1080p format at 60 fps and at the cost of 10.0 kALUTs and 216 DSP blocks. The respective figures for the proposed high-speed variant are 2160p at 30 fps with 13.9 kALUTs and 344 DSP blocks. These cost-performance characteristics outperform respective non-HLS approaches on FPGA.
    AlkuperäiskieliEnglanti
    OtsikkoProceedings of 2017 IEEE International Conference on Acoustics, Speech and Signal Processing
    KustantajaIEEE
    Sivut1547-1551
    ISBN (elektroninen)978-1-5090-4117-6
    DOI - pysyväislinkit
    TilaJulkaistu - 2017
    OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisussa
    TapahtumaIEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING -
    Kesto: 1 tammikuuta 19001 tammikuuta 2000

    Julkaisusarja

    Nimi
    ISSN (elektroninen)2379-190X

    Conference

    ConferenceIEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING
    Ajanjakso1/01/001/01/00

    Julkaisufoorumi-taso

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