High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA

    Tutkimustuotos: Conference contributionScientificvertaisarvioitu

    3 Sitaatiot (Scopus)
    23 Lataukset (Pure)

    Abstrakti

    This paper presents efficient inverse discrete cosine transform (IDCT) and inverse discrete sine transform (IDST) implementations for High Efficiency Video Coding (HEVC). The proposal makes use of high-level synthesis (HLS) to implement a complete HEVC 2-D IDCT/IDST architecture directly from the C code of a well-known Even-Odd decomposition algorithm. The final architecture includes a 4-point IDCT/IDST unit for the smallest transform blocks (TB), an 8/16/32-point IDCT unit for the other TBs, and a transpose memory for intermediate results. On Arria II FPGA, it supports real-time (60 fps) HEVC decoding of up to 2160p format with 12.4 kALUTs and 344 DSP blocks. Compared with the other existing HLS approach, the proposed solution is almost 5 times faster and is able to utilize available FPGA resources better.
    AlkuperäiskieliEnglanti
    OtsikkoProceedings of 2017 IEEE International Symposium on Circuits and Systems
    KustantajaIEEE
    Sivut1-4
    ISBN (elektroninen)978-1-4673-6853-7
    DOI - pysyväislinkit
    TilaJulkaistu - 2017
    OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisussa
    TapahtumaIEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS -
    Kesto: 1 tammikuuta 1900 → …

    Julkaisusarja

    Nimi
    ISSN (elektroninen)2379-447X

    Conference

    ConferenceIEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
    Ajanjakso1/01/00 → …

    Julkaisufoorumi-taso

    • Jufo-taso 1

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