High speed DC-DC dead time architecture

Jani Järvenhaara; Hans Herzog; Sami Sipilä; Jing Tian; Igor M. Filanovsky; Nikolay T. Tchamov

doi:10.1587/elex.12.20150662

High speed DC-DC dead time architecture

Jani Järvenhaara, Hans Herzog, Sami Sipilä, Jing Tian, Igor M. Filanovsky, Nikolay T. Tchamov

Tutkimustuotos: Artikkeli › Tieteellinen › vertaisarvioitu

4 Sitaatiot (Scopus)

Abstrakti

A novel and simple solution for adjusting dead time in high speed DC-DC converters is proposed. The usual dead time adjustment of DC-DC converters through feedback control has limited speed. For the high speed converters extra circuitry and delays in the feedback should be minimized. A 240 MHz DC-DC converter with the presented dead time circuit is designed on low-voltage fast CMOS process.

Alkuperäiskieli	Englanti
Artikkeli	20150662
Julkaisu	IEICE Electronics Express
Vuosikerta	12
Numero	19
DOI - pysyväislinkit	https://doi.org/10.1587/elex.12.20150662
Tila	Julkaistu - 10 lokak. 2015
OKM-julkaisutyyppi	A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä

Julkaisufoorumi-taso

Jufo-taso 1

!!ASJC Scopus subject areas

Electrical and Electronic Engineering

Pääsy asiakirjaan

10.1587/elex.12.20150662

Siteeraa tätä

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title = "High speed DC-DC dead time architecture",

abstract = "A novel and simple solution for adjusting dead time in high speed DC-DC converters is proposed. The usual dead time adjustment of DC-DC converters through feedback control has limited speed. For the high speed converters extra circuitry and delays in the feedback should be minimized. A 240 MHz DC-DC converter with the presented dead time circuit is designed on low-voltage fast CMOS process.",

keywords = "DC-DC converters, cascode, dead time auto-generation",

author = "Jani J{\"a}rvenhaara and Hans Herzog and Sami Sipil{\"a} and Jing Tian and Filanovsky, {Igor M.} and Tchamov, {Nikolay T.}",

year = "2015",

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day = "10",

doi = "10.1587/elex.12.20150662",

language = "English",

volume = "12",

journal = "IEICE Electronics Express",

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publisher = "The Institute of Electronics, Information and Communication Engineers (IEICE)",

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TY - JOUR

T1 - High speed DC-DC dead time architecture

AU - Järvenhaara, Jani

AU - Herzog, Hans

AU - Sipilä, Sami

AU - Tian, Jing

AU - Filanovsky, Igor M.

AU - Tchamov, Nikolay T.

PY - 2015/10/10

Y1 - 2015/10/10

N2 - A novel and simple solution for adjusting dead time in high speed DC-DC converters is proposed. The usual dead time adjustment of DC-DC converters through feedback control has limited speed. For the high speed converters extra circuitry and delays in the feedback should be minimized. A 240 MHz DC-DC converter with the presented dead time circuit is designed on low-voltage fast CMOS process.

AB - A novel and simple solution for adjusting dead time in high speed DC-DC converters is proposed. The usual dead time adjustment of DC-DC converters through feedback control has limited speed. For the high speed converters extra circuitry and delays in the feedback should be minimized. A 240 MHz DC-DC converter with the presented dead time circuit is designed on low-voltage fast CMOS process.

KW - DC-DC converters

KW - cascode

KW - dead time auto-generation

U2 - 10.1587/elex.12.20150662

DO - 10.1587/elex.12.20150662

M3 - Article

SN - 1349-2543

VL - 12

JO - IEICE Electronics Express

JF - IEICE Electronics Express

IS - 19

M1 - 20150662

ER -

High speed DC-DC dead time architecture

Abstrakti

Julkaisufoorumi-taso

!!ASJC Scopus subject areas

Pääsy asiakirjaan

Sormenjälki

Siteeraa tätä