Implementation of IEEE-802.11a/g receiver blocks on a coarse-grained reconfigurable array

This paper presents the implementation of Orthogonal Frequency-Division Multiplexing receiver blocks as accelerators using a template-based Coarse-Grained Reconfigurable Array (CGRA) device. The CGRA operates with a Reduced Instruction-Set Computing (RISC) processor so that the overall system yields the benefits of general-and special-purpose processing. The accelerators are designed by crafting the CGRA template to the computational and communication requirements of the algorithms in an effort to minimize the resource utilization and power dissipation on the target Field Programmable Gate Array (FPGA) device. The accelerators are also evaluated for performance in terms of the number of clock cycles, resource utilization, synthesis frequency, power and energy estimation. The implementation results show that the designed accelerators give speed-up of 2.8X to 9.3X in comparison with a RISC software implementation.