Parallel Algorithms and VLSI Architectures for Stack Filtering Using Fibonacci p-Codes

Julkaisun otsikon käännös: Parallel Algorithms and VLSI Architectures for Stack Filtering Using Fibonacci p-Codes

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Julkaisun otsikon käännös	Parallel Algorithms and VLSI Architectures for Stack Filtering Using Fibonacci p-Codes
Alkuperäiskieli	Englanti
Sivut	286-295
Julkaisu	IEEE Transactions on Signal Processing
Vuosikerta	43
Numero	1
Tila	Julkaistu - 1995
OKM-julkaisutyyppi	A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä

Julkaisufoorumi-taso

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title = "Parallel Algorithms and VLSI Architectures for Stack Filtering Using Fibonacci p-Codes",

author = "Gevorgian, \{D. Z.\} and Egiazarian, \{K. O.\} and Agaian, \{S. S.\} and Astola, \{J. T.\} and O. Vainio",

note = "Contribution: organisation=sgn,FACT1=1<br/>Publisher name: Institute of Electrical and Electronics Engineers IEEE",

year = "1995",

language = "English",

volume = "43",

pages = "286--295",

journal = "IEEE Transactions on Signal Processing",

issn = "1053-587X",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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TY - JOUR

T1 - Parallel Algorithms and VLSI Architectures for Stack Filtering Using Fibonacci p-Codes

AU - Gevorgian, D. Z.

AU - Egiazarian, K. O.

AU - Agaian, S. S.

AU - Astola, J. T.

AU - Vainio, O.

N1 - Contribution: organisation=sgn,FACT1=1<br/>Publisher name: Institute of Electrical and Electronics Engineers IEEE

PY - 1995

Y1 - 1995

M3 - Article

SN - 1053-587X

VL - 43

SP - 286

EP - 295

JO - IEEE Transactions on Signal Processing

JF - IEEE Transactions on Signal Processing

IS - 1

ER -