Programmable and Scalable Architecture for Graphics Processing Units

Carlos S. de La Lama; Pekka Jääskeläinen; Heikki Kultala; Jarmo Takala

doi:10.1007/978-3-662-58834-5_2

Programmable and Scalable Architecture for Graphics Processing Units

Carlos S. de La Lama, Pekka Jääskeläinen, Heikki Kultala, Jarmo Takala

Tietotekniikka

Tutkimustuotos: Luku › Scientific › vertaisarvioitu

Abstrakti

Graphics processing is an application area with high level of parallelism at the data level and at the task level. Therefore, graphics processing units (GPU) are often implemented as multiprocessing systems with high performance floating point processing and application specific hardware stages for maximizing the graphics throughput.

In this paper we evaluate the suitability of Transport Triggered Architectures (TTA) as a basis for implementing GPUs. TTA improves scalability over the traditional VLIW-style architectures making it interesting for computationally intensive applications. We show that TTA provides high floating point processing performance while allows more programming freedom than vector processors.

Finally, one of the main features of the presented TTA-based GPU design is its fully programmable architecture making it a suitable target for general purpose computing on GPU APIs which have become popular in the recent years.

Alkuperäiskieli	Englanti
Otsikko	Transactions on High-Performance Embedded Architectures and Compilers V
Toimittajat	Per Stenström, Cristina Silvano, Koen Bertels, Mike Schulte
Sivut	21-38
ISBN (elektroninen)	978-3-662-58834-5
DOI - pysyväislinkit	https://doi.org/10.1007/978-3-662-58834-5_2
Tila	Julkaistu - 23 helmik. 2019
OKM-julkaisutyyppi	A3 Kirjan tai muun kokoomateoksen osa

Julkaisusarja

Nimi	Lecture Notes in Computer Science
Kustantaja	Springer
Vuosikerta	11225
ISSN (painettu)	0302-9743
ISSN (elektroninen)	1611-3349

Julkaisufoorumi-taso

Jufo-taso 1

Pääsy asiakirjaan

10.1007/978-3-662-58834-5_2Lisenssi: Unspecified

Siteeraa tätä

de La Lama, C. S., Jääskeläinen, P., Kultala, H., & Takala, J. (2019). Programmable and Scalable Architecture for Graphics Processing Units. teoksessa P. Stenström, C. Silvano, K. Bertels, & M. Schulte (Toimittajat), Transactions on High-Performance Embedded Architectures and Compilers V (Sivut 21-38). (Lecture Notes in Computer Science; Vuosikerta 11225). https://doi.org/10.1007/978-3-662-58834-5_2

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de La Lama, CS, Jääskeläinen, P, Kultala, H & Takala, J 2019, Programmable and Scalable Architecture for Graphics Processing Units. julkaisussa P Stenström, C Silvano, K Bertels & M Schulte (toim), Transactions on High-Performance Embedded Architectures and Compilers V. Lecture Notes in Computer Science, Vuosikerta 11225, Sivut 21-38. https://doi.org/10.1007/978-3-662-58834-5_2

Programmable and Scalable Architecture for Graphics Processing Units. / de La Lama, Carlos S.; Jääskeläinen, Pekka; Kultala, Heikki et al.
Transactions on High-Performance Embedded Architectures and Compilers V. toim. / Per Stenström; Cristina Silvano; Koen Bertels; Mike Schulte. 2019. s. 21-38 (Lecture Notes in Computer Science; Vuosikerta 11225).

Tutkimustuotos: Luku › Scientific › vertaisarvioitu

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Programmable and Scalable Architecture for Graphics Processing Units

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