Taylor Series Based Method for Generating Digital Sine and Cosine Signals on an FPGA

In this paper, we are presenting method for generating digitally sine and cosine signals by applying Taylor series approximation. The methodology is commonly referred to as direct digital frequency synthesis (DDFS), and it is used today in various communication systems since it provides fast and precise frequency tuning, low phase noise, and low latency. The proposed method consumes minimal memory, and we are demonstrating how it is efficiently implemented on a field-programmable gate array (FPGA). Improving the output signal purity using two different dithering methods is also analyzed. Based on the implementation results, the proposed architecture with dithering is capable of reaching -81.04 dBc spurious free dynamic range (SFDR). On an FPGA, the design consumes 298 look-up tables (LUT) in 104 slices.