Visualization of memory map information in embedded system design

Mikko Teuho; Esko Pekkarinen; Timo D. Hämäläinen

doi:10.1109/DSD.2018.00040

Visualization of memory map information in embedded system design

Mikko Teuho, Esko Pekkarinen, Timo D. Hämäläinen

Tutkimustuotos: Konferenssiartikkeli › Tieteellinen › vertaisarvioitu

Abstrakti

Data compression is a common requirement for displaying large amounts of information. The goal is to reduce visual clutter. The approach given in this paper uses an analysis of a data set to construct a visual representation. The visualization is compressed using the address ranges of the memory structure. This method produces a compressed version of the initial visualization, retaining the same information as the original. The presented method has been implemented as a Memory Designer tool for ASIC, FPGA and embedded systems using IP-XACT. The Memory Designer is a user-friendly tool for model based embedded system design, providing access and adjustment of the memory layout from a single view, complementing the 'programmer's view' to the system.

Alkuperäiskieli	Englanti
Otsikko	Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018
Kustantaja	IEEE
Sivut	163-166
Sivumäärä	4
ISBN (elektroninen)	9781538673768
DOI - pysyväislinkit	https://doi.org/10.1109/DSD.2018.00040
Tila	Julkaistu - 12 lokak. 2018
OKM-julkaisutyyppi	A4 Artikkeli konferenssijulkaisussa
Tapahtuma	Euromicro Conference on Digital System Design - Prague, Tshekki Kesto: 29 elok. 2018 → 31 elok. 2018

Conference

Conference	Euromicro Conference on Digital System Design
Maa/Alue	Tshekki
Kaupunki	Prague
Ajanjakso	29/08/18 → 31/08/18

Julkaisufoorumi-taso

Jufo-taso 1

!!ASJC Scopus subject areas

Hardware and Architecture

Pääsy asiakirjaan

10.1109/DSD.2018.00040

Siteeraa tätä

@inproceedings{678dffd41aad4a3ba608d9b7c75bd650,

title = "Visualization of memory map information in embedded system design",

abstract = "Data compression is a common requirement for displaying large amounts of information. The goal is to reduce visual clutter. The approach given in this paper uses an analysis of a data set to construct a visual representation. The visualization is compressed using the address ranges of the memory structure. This method produces a compressed version of the initial visualization, retaining the same information as the original. The presented method has been implemented as a Memory Designer tool for ASIC, FPGA and embedded systems using IP-XACT. The Memory Designer is a user-friendly tool for model based embedded system design, providing access and adjustment of the memory layout from a single view, complementing the 'programmer's view' to the system.",

keywords = "Compression, Data visualization, Display space, Filtering, Memory structure",

author = "Mikko Teuho and Esko Pekkarinen and H{\"a}m{\"a}l{\"a}inen, {Timo D.}",

year = "2018",

month = oct,

day = "12",

doi = "10.1109/DSD.2018.00040",

language = "English",

pages = "163--166",

booktitle = "Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018",

publisher = "IEEE",

address = "United States",

note = "Euromicro Conference on Digital System Design ; Conference date: 29-08-2018 Through 31-08-2018",

}

TY - GEN

T1 - Visualization of memory map information in embedded system design

AU - Teuho, Mikko

AU - Pekkarinen, Esko

AU - Hämäläinen, Timo D.

PY - 2018/10/12

Y1 - 2018/10/12

N2 - Data compression is a common requirement for displaying large amounts of information. The goal is to reduce visual clutter. The approach given in this paper uses an analysis of a data set to construct a visual representation. The visualization is compressed using the address ranges of the memory structure. This method produces a compressed version of the initial visualization, retaining the same information as the original. The presented method has been implemented as a Memory Designer tool for ASIC, FPGA and embedded systems using IP-XACT. The Memory Designer is a user-friendly tool for model based embedded system design, providing access and adjustment of the memory layout from a single view, complementing the 'programmer's view' to the system.

AB - Data compression is a common requirement for displaying large amounts of information. The goal is to reduce visual clutter. The approach given in this paper uses an analysis of a data set to construct a visual representation. The visualization is compressed using the address ranges of the memory structure. This method produces a compressed version of the initial visualization, retaining the same information as the original. The presented method has been implemented as a Memory Designer tool for ASIC, FPGA and embedded systems using IP-XACT. The Memory Designer is a user-friendly tool for model based embedded system design, providing access and adjustment of the memory layout from a single view, complementing the 'programmer's view' to the system.

KW - Compression

KW - Data visualization

KW - Display space

KW - Filtering

KW - Memory structure

U2 - 10.1109/DSD.2018.00040

DO - 10.1109/DSD.2018.00040

M3 - Conference contribution

AN - SCOPUS:85056487173

SP - 163

EP - 166

BT - Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018

PB - IEEE

T2 - Euromicro Conference on Digital System Design

Y2 - 29 August 2018 through 31 August 2018

ER -

Visualization of memory map information in embedded system design

Abstrakti

Conference

Julkaisufoorumi-taso

!!ASJC Scopus subject areas

Pääsy asiakirjaan

Sormenjälki

Siteeraa tätä