Visualization of memory map information in embedded system design

    Tutkimustuotos: Conference contributionScientificvertaisarvioitu

    Abstrakti

    Data compression is a common requirement for displaying large amounts of information. The goal is to reduce visual clutter. The approach given in this paper uses an analysis of a data set to construct a visual representation. The visualization is compressed using the address ranges of the memory structure. This method produces a compressed version of the initial visualization, retaining the same information as the original. The presented method has been implemented as a Memory Designer tool for ASIC, FPGA and embedded systems using IP-XACT. The Memory Designer is a user-friendly tool for model based embedded system design, providing access and adjustment of the memory layout from a single view, complementing the 'programmer's view' to the system.

    AlkuperäiskieliEnglanti
    OtsikkoProceedings - 21st Euromicro Conference on Digital System Design, DSD 2018
    KustantajaIEEE
    Sivut163-166
    Sivumäärä4
    ISBN (elektroninen)9781538673768
    DOI - pysyväislinkit
    TilaJulkaistu - 12 lokakuuta 2018
    OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisussa
    TapahtumaEuromicro Conference on Digital System Design - Prague, Tshekki
    Kesto: 29 elokuuta 201831 elokuuta 2018

    Conference

    ConferenceEuromicro Conference on Digital System Design
    Maa/AlueTshekki
    KaupunkiPrague
    Ajanjakso29/08/1831/08/18

    Julkaisufoorumi-taso

    • Jufo-taso 1

    !!ASJC Scopus subject areas

    • Hardware and Architecture

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